PIC16F627-04/P【PDF 118/170 页】IC MCU FLASH 1KX14 COMP 18DIP

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Sheet目录3873

114页 115页 116页 117页 [118页]119页 120页 121页 122页

2003 Microchip Technology Inc.

Preliminary

DS40300C-page 49

PIC16F62X

7.4

Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The oscilla-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 7-1 shows the capacitor

selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.

The user must provide a software time delay to ensure

proper oscillator start-up.

TABLE 7-1:

CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

7.5

Resetting Timer1 Using a CCP

Trigger Output

If the CCP1 module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will reset Timer1.

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this RESET operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPRxH:CCPRxL

registers pair effectively becomes the period register

for Timer1.

7.6

Resetting of Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H and TMR1L registers are not reset to 00h on a

POR or any other RESET except by the CCP1 special

event triggers.

T1CON register is reset to 00h on a Power-on Reset or

a Brown-out Reset, which shuts off the timer and

leaves a 1:1 prescale. In all other RESETS, the register

is unaffected.

7.7

Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 7-2:

REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Osc Type

Freq

32 kHz

33 pF

100 kHz

15 pF

200 kHz

15 pF

Note 1: These values are for design guidance only.

Consult AN826 (DS00826A) for further

information on Crystal/Capacitor Selection.

Note:

The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Value on

all other

RESETS

0Bh/8Bh/

10Bh/18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

EEIF

CMIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF

0000 -000

8Ch

PIE1

EEIE

CMIE

RCIE

TXIE

—

CCP1IE

TMR2IE

TMR1IE

0000 -000

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

—

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

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